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| DATASHEET LOW PHASE NOISE T1/E1 CLOCK GENERATOR Description The MK1581-01 provides synchronization and timing control for T1 and E1 based network access or multitrunk telecommunication systems. The device accepts an 8 kHz frame clock input and uses an on-chip VCXO to produce a synchronized low phase noise clock output. This monolithic IC, combined with an external inexpensive quartz crystal, can be used to replace a more costly hybrid VCXO retiming module. Through selection of external loop filter components values, the device can be tailored to meet the system's clock jitter attenuation requirements. Low-pass jitter attenuation characteristics in the Hz range are possible. MK1581-01 Features * Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output * * * * * * * * clock from an 8kHz frame clock input Configurable jitter attenuation characteristics, excellent for use as a Stratum source de-jitter circuit VCXO-based clock generation ensures very low jitter and phase noise generation Output clock is phase and frequency locked to the input reference clock +115ppm minimum crystal frequency pullability range, using recommended crystal Industrial temperature range Low power CMOS technology 16 pin TSSOP package Single 3.3 V power supply Block Diagram RSET Pullable Crystal X1 X2 VDD VDD 3 ISET Phase Detector 8kHz_IN Charge Pump VCXO Output Divider CLK Feedback Divider SEL CHGP RS CS VIN GND 5 CP IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 1 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Pin Assignment VDD VDD VDD VIN GND GND GND CHGP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X1 X2 8kHz_IN SEL CLK GND GND ISET Output Clock Selection Table Input Clock 8 kHz 8 kHz SEL 0 1 Output Clock (MHz) 1.544 2.048 Crystal Used (MHz) 24.704 24.576 16 pin 4.40 mil body, 0.65 mm pitch TSSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VDD VDD VDD VIN GND GND GND CHGP ISET GND GND CLK SEL 8kHz_IN X2 X1 Pin Type Power Power Power Input Power Power Power Output - Power Power Output Input Input - - Pin Description Power Supply. Connect to +3.3 V. Power Supply. Connect to +3.3 V. Power Supply. Connect to +3.3 V. VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop filter as shown in this data sheet. Connect to ground. Connect to ground. Connect to ground. Charge Pump Output. Connect this pin to the external loop filter and to pin VIN. Charge pump current setting node, connection for setting resistor. Connect to ground. Connect to ground. Clock Output. Output Frequency Selection. Determines output frequency as per table above. Internal pull-up. 8 kHz reference clock input. Crystal Output. Connect this pin to the specified crystal. Crystal Input. Connect this pin to the specified crystal. IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 2 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Functional Description The MK1581-01 is a clock generator IC that generates a T1 or E1 reference clock directly from an internal VCXO circuit that works in conjunction with an external quartz crystal. The VCXO output frequency and phase is controlled by an internal PLL (Phase Locked Loop) circuit, enabling the device to perform clock regeneration from an 8 kHz input reference clock. Most typical PLL clock devices use an internal VCO (Voltage Controlled Oscillator) for output clock generation. By using a VCXO with an external crystal, the MK1581-01 is able to generate a low jitter, low phase-noise output clock. The low bandwidth capability of the PLL circuit serves to provide input clock jitter attenuation and enables stable operation with the low frequency input reference clock. The internal VCXO circuit requires an external pullable crystal for operation. External loop filter components enable a PLL configuration with low loop bandwidth. The frequency of oscillation of a quartz crystal is determined by its cut and by the external load capacitance. The MK1581-01 incorporates variable load capacitors on-chip which "pull", or change, the frequency of the crystal. The crystals specified for use with the MK1581-01 are designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. To achieve this, the layout should use short traces between the MK1581-01 and the crystal. A complete description of the recommended crystal parameters is in application note MAN05. A list of approved crystals is located on the IDT web site (www.idt.com). PLL Loop Filter Components A phased-locked loop (PLL) is a control system that keeps the VCO frequency and phase locked with the input reference clock. Like all control systems, analog PLL circuits use a loop filter to establish operating stability. The MK1581-01 uses external loop filter components for the following reasons: 1) Larger loop filter capacitor values can be used, allowing a lower loop bandwidth. This enables the use of lower input clock reference frequencies and also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking is desired. 2) The loop filter values can be user selected to optimize loop response characteristics for a given application. Referencing the External Component Schematic on this page, the external loop filter is made up of components RS, CS and CP. RSET establishes PLL charge pump current and therefore influences loop filter characteristics. Design aid tools for configuring the loop filter can be found at www.idt.com, including on-line and PC-based calculators. Application Information Output Frequency Configuration The MK1581-01 is configured to generate either a 1.544 MHz T1 clock or a 2.048 MHz E1 clock from an 8 kHz input clock. Please refer to the Output Clock Selection Table on Page 2. Input bit SEL is set according to this table, as is the external crystal frequency. Please refer to the Quartz Crystal section on this page regarding external crystal requirements. Quartz Crystal It is important that the correct type of quartz crystal is used with the MK1581-01. Failure to do so may result in reduced frequency pullability range, inability of the loop to lock, or excessive output phase jitter. The MK1581-01 operates by phase-locking the VCXO circuit to the input signal of the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the PCB Layout Recommendations section must be followed. IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 3 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER External Component Schematic Refer to Crystal Tuning section CL CL CP VDD VDD VDD VIN GND RS GND GND CS CHGP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X1 X2 8kHz_IN SEL CLK GND GND ISET Pullable Crystal RSET Recommended Loop Filter Values Vs. Output Frequency Selection Crystal SEL Output Freq Multiplier (N) 0 1 1.544 MHz 2.048 MHz 3088 3072 RSET 120 k 120 k RS 1.0 M 1.0 M CS 0.1 F 0.1 F CP 4.7 nF 4.7 nF Loop Bandwidth (-3dB point) Damping Factor 1.4 1.4 18 Hz 19 Hz IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 4 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER A "normalized" PLL loop bandwidth may be calculated as follows: Charge Pump Current Table R S x I CP x 575 NBW = ----------------------------------------N RSET 1.4 M 680 k 540 k 120 k Charge Pump Current (ICP) 10 A 20 A 25 A 100 A The "normalized" bandwidth (NBW) equation above does not take into account the effects of damping factor or the second pole. NBW is approximately equal to the actual -3dB bandwidth of the loop when the damping factor is about 5 and C2 is very small. In most applications, NBW is about 75% of the actual -3dB bandwidth. However, NBW does provide a useful approximation of filter performance. The loop damping factor is calculated as follows: Special considerations must be made in choosing loop components CS and CP. These recommendations can be found in the design aid tools section of www.icst.com. Series Termination Resistor Damping Factor = R S x 625 x I CP x C S -----------------------------------------N Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20 (The . optional series termination resistor is not shown in the External Component Schematic.) Where: RS = Value of resistor in loop filter (Ohms) ICP = Charge pump current (amps) (refer to Charge Pump Current Table, below) N = Crystal multiplier shown in the above table CS = Value of capacitor CS in loop filter (Farads) As a general rule, the following relationship should be maintained between components CS and CP in the loop filter: Decoupling Capacitors As with any high performance mixed-signal IC, the MK1581-01 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the MK1581-01 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. CP S = ----- C 20 IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 5 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Recommended Power Supply Connection for Optimal Device Performance V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead V D D P in from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 4) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the MK1581-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The IDT Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. B ulk D ecoupling C apacitor (such as 1 F Tantalum ) V D D P in 0.01 F D ecoupling C apacitors Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground, shown as CL in the External Component Schematic. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. In most cases the load capacitors will not be required. They should not be stuffed on the prototype evaluation board as the indiscriminate use of these trim capacitors will typically cause more crystal centering error than their absence. If the need for the load capacitors is later determined, the values will fall within the 1-4 pF range. The need for, and value of, these trim capacitors can only be determined at prototype evaluation. Refer to MAN05 for the centering capacitor selection procedure. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please also refer to the Recommended PCB Layout drawing on Page 7. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via's should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 6 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Recommended PCB Layout For m inim um output clock jitter, device V D D connections should be m ade to com m on bulk decoupling device (see text). G For m inim um output clock jitter, rem ove ground and pow er plane w ithin this entire area. A lso route all other traces aw ay from this area. G 1 16 15 14 13 12 11 10 G G 2 3 4 5 6 7 8 G G G G G 9 G Legend: G = G round C onnection Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1581-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V -40 to +85 C -65 to +150 C 125 C 260 C IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 7 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. -40 +3.15 Typ. +3.3 Max. +85 +3.45 Units C V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C Parameter Operating Voltage Supply Current Input High Voltage, SEL Input Low Voltage, SEL Input High Voltage, 8kHz_IN Input Low Voltage, 8kHz_IN Input High Current Input Low Current Input Capacitance, except X1 Output High Voltage (CMOS Level) Output High Voltage Output Low Voltage Short Circuit Current VIN, VCXO Control Voltage Nominal Output Impedance Symbol VDD IDD VIH VIL VIH VIL IIH IIL CIN VOH VOH VOL IOS VXC ZOUT Conditions Clock outputs unloaded, VDD = 3.3 V Min. 3.15 Typ. 3.3 10 Max. 3.45 15 Units V mA V 2 0.8 VDD/2+1 VDD/2-1 V V V A A pF V V VIH = VDD VIL = 0 IOH = -4 mA IOH = -8 mA IOL = 8 mA -10 -10 7 VDD-0.4 2.4 +10 +10 0.4 50 0 20 VDD V mA V AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C Parameter VCXO Crystal Pull Range VCXO Crystal Nominal Frequency Input Jitter Tolerance Input pulse width (1) Output Frequency Error Output Duty Cycle (% high time) Symbol fXP fX tji tpi FOUT tOD Conditions Using Recommended Crystal Min. -115 24.704 Typ. Max. +115 24.576 0.4 Units ppm MHz UI ns In reference to input clock period 10 ICLK = 0 ppm error Measured at VDD/2, CL=15 pF 0 40 0 0 60 ppm % IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 8 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Parameter Output Rise Time Output Fall Time Skew, Input to Output Clock Cycle Jitter (short term jitter) Symbol tOR tOF tIO tja Conditions 0.8 to 2.0V, CL=15 pF 2.0 to 0.8V, CL=15 pF Note 2 Peak to Peak Min. Typ. Max. 1.5 1.5 Units ns ns ps p-p 150 Note 1: Minimum high or low time of input clock. Note 2: The input to output clock skew is not controlled nor predictable and will change between power up cycles. Because it is dependent on the phase relationship between the output and feedback divider states following power up, the input to output clock skew will remain stable during a given power up cycle. If controlled input to output skew is desired for this output clock frequency please refer to the MK2049 or MK2069 products. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 78 70 68 37 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 9 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters Symbol Min Max Inches Min Max 16 E1 IN D EX AR EA E 1 2 D A A1 A2 b C D E E1 e L aaa -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A 2 A 1 A c -Ce b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number MK1581-01GI MK1581-01GITR MK1581-01GILF MK1581-01GILFTR Marking MK1581-01GI MK1581-01GI 15810GIL 15810GIL Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Temperature -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM LOW PHASE NOISE T1/E1 CLOCK GENERATOR 10 MK1581-01 REV D 073007 MK1581-01 LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-4522 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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